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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer'sTM Data Sheet
TMOS E-FET.TM Power Field Effect Transistor
N-Channel Enhancement-Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain-to-source diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters, PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature
D
MTY55N20E
Motorola Preferred Device
TMOS POWER FET 55 AMPERES 200 VOLTS RDS(on) = 0.028 OHM
(R)
G S Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg EAS RJC RJA TL
CASE 340G-02, STYLE 1 TO-264
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1 M) Gate-Source Voltage -- Continuous Gate-Source Voltage -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous @ TC = 25C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 110 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
Value 200 200 20 40 55 165 300 2.38 - 55 to 150 3000 0.42 40 260
Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ C/W C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
E-FET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
(c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1995
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MTY55N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 250 A) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 27.5 Adc) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 55 Adc) (ID = 27.5 Adc, TJ = 125C) Forward Transconductance (VDS = 10 Vdc, ID = 27.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 160 Vdc, ID = 55 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 55 Adc, VGS = 10 Vdc, RG = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 55 Adc, VGS = 0 Vdc) (IS = 55 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr (IS = 55 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD LS -- -- 4.5 13 -- -- nH nH ta tb QRR -- -- -- -- 0.75 1.1 310 220 90 4.6 1.2 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 33 200 150 170 245 33 128 79 66 400 300 340 343 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1 MHz) Ciss Coss Crss -- -- -- 7200 1800 460 10080 2520 920 pF VGS(th) 2 -- RDS(on) VDS(on) -- -- gFS 30 1.3 -- 37 1.6 1.8 -- mhos -- -- 7 -- 4 -- 0.028 Vdc mV/C Ohm Vdc V(BR)DSS 200 -- IDSS -- -- IGSS -- -- -- -- 10 200 100 nAdc -- 250 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 14)
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Motorola TMOS Power MOSFET Transistor Device Data
MTY55N20E
TYPICAL ELECTRICAL CHARACTERISTICS
120 TJ = 25C I D , DRAIN CURRENT (AMPS) 100 9V 80 6V 60 40 5V 20 4V 0 0 0.5 1 1.5 2 2.5 3 3.5 4 0 2 2.5 3 3.5 4 4.5 5 VGS = 10 V 8V 7V I D , DRAIN CURRENT (AMPS) 100 80 60 40 100C 20 TJ = - 55C 25C 5.5 6 6.5 7 120 VDS 10 V
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.05 VGS = 10 V 0.04 TJ = 100C
0.027 TJ = 25C 0.026 VGS = 10 V
0.03 25C 0.02 - 55C 0.01
0.025
0.024 15 V 0.023
0
0
20
40
60
80
100
120
0.022
0
20
40
60
80
100
120
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 - 50 - 25 0 25 50 75 100 125 150 VGS = 10 V ID = 27.5 A
10000 VGS = 0 V 1000 I DSS , LEAKAGE (nA) TJ = 125C
100C
100
10
25C
1
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
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MTY55N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
24000 VDS = 0 V 20000 C, CAPACITANCE (pF) 16000 12000 8000 Coss 4000 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 Crss Ciss Ciss VGS = 0 V TJ = 25C
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTY55N20E
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 50 100 150 VDS 200 Qg, TOTAL GATE CHARGE (nC) Q2 Q1 TJ = 25C ID = 55 A 240 200 VGS 160 120 80 40 0 250 1000 VDD = 100 V ID = 55 A VGS = 10 V TJ = 25C t, TIME (ns)
QT
100
tr tf td(off)
td(on) 10
1
10 RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate Charge versus Gate-to-Source Voltage
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
60 50 I S , SOURCE CURRENT (AMPS) 40 30 20 10 0 0.5 VGS = 0 V TJ = 25C
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
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MTY55N20E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 100 10 s 100 s RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 1 10 1 ms 10 ms dc 100 1000 E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 3000 ID = 55 A
2000
10
1000
0
25
50
75
100
125
150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1 D = 0.5 0.2 0.1 0.1 0.02 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 0.05 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
0.01 1.0E-05
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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Motorola TMOS Power MOSFET Transistor Device Data
MTY55N20E
PACKAGE DIMENSIONS
0.25 (0.010) -B- -Q-
M
TB
M
-T- C
U N A R -Y- P K
1 2 3
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 2.8 2.9 19.3 20.3 4.7 5.3 0.93 1.48 1.9 2.1 2.2 2.4 5.45 BSC 2.6 3.0 0.43 0.78 17.6 18.8 11.0 11.4 3.95 4.75 2.2 2.6 3.1 3.5 2.15 2.35 6.1 6.5 2.8 3.2 INCHES MIN MAX 1.102 1.142 0.760 0.800 0.185 0.209 0.037 0.058 0.075 0.083 0.087 0.102 0.215 BSC 0.102 0.118 0.017 0.031 0.693 0.740 0.433 0.449 0.156 0.187 0.087 0.102 0.122 0.137 0.085 0.093 0.240 0.256 0.110 0.125
L
F 2 PL G
W D 3 PL 0.25 (0.010)
M
J H YQ
S
DIM A B C D E F G H J K L N P Q R U W
STYLE 1: PIN 1. GATE 2. DRAIN 3. SOURCE
CASE 340G-02 TO-264 ISSUE E
Motorola TMOS Power MOSFET Transistor Device Data
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MTY55N20E
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Motorola TMOS Power MOSFET Transistor Device Data MTY55N20E/D
*MTY55N20E/D*

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